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[Other resourceddr_verilog_xilinx

Description: DDR(双速率)SDRAM控制器参考设计,xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131327 | Author: 陈旭 | Hits:

[File OperateDDR_SDRAM_use_in_embedded

Description: 很多嵌入式系统,特别是应用于图像处理与高速数据采集等场合的嵌入式系统,都需要高速缓存大量的数据。DDR(Double Data Rate,双数据速率)SDRAM由于其速度快、容量大,而且价格便宜,因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连,需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Platform: | Size: 237546 | Author: joucan | Hits:

[Other resourceDDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码,实现平台是Lattice FPGA,功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 678583 | Author: 钟方 | Hits:

[Other resourcexapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps(333 MHz)高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器(ISERDES)和输出串行器/解串器(OSERDES)的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input / Solution Series (ISERDES) and serial output / Solution Series (O Legacy) function.
Platform: | Size: 297475 | Author: mingming | Hits:

[Otherddr_ctrlv

Description: ddr ram controller vhdl code
Platform: | Size: 55711 | Author: heyong | Hits:

[Software EngineeringDDR2deFPGAsheji

Description: 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
Platform: | Size: 2525184 | Author: 张桃源 | Hits:

[VHDL-FPGA-VerilogDDRSDRAM

Description: 用vdhl编写的DDR sdram控制器,采用模块化编写,条理清楚,注解详细,附有存储器的说明。-the ddr sdram controller base vhdl
Platform: | Size: 476160 | Author: tangjieling | Hits:

[VHDL-FPGA-Verilogsram

Description: sram操作vhdl源程序,内有sdram模型,控制器设计,及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

[VHDL-FPGA-Verilogddr_sdr

Description: ddr ram控制器,使用vhdl语言实现-ddr ram controller,designed by vhdl
Platform: | Size: 115712 | Author: | Hits:

[VHDL-FPGA-Verilogsdram_vhdl

Description: DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Platform: | Size: 891904 | Author: 薛鹏展 | Hits:

[VHDL-FPGA-Verilogug230.pdf

Description: The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific features • Parallel NOR Flash configuration • MultiBoot FPGA configuration from Parallel NOR Flash PROM • SPI serial Flash configuration • Embedded development • MicroBlazeTM 32-bit embedded RISC processor • PicoBlazeTM 8-bit embedded controller • DDR memory interfaces
Platform: | Size: 5851136 | Author: Akalu Lentiro | Hits:

[VHDL-FPGA-Verilogddr_sdr_latest[1].tar

Description: ddr sdram 控制器的接口,为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
Platform: | Size: 80896 | Author: hxr | Hits:

[SCMug_ddr_sdram

Description: DDR and DDR2 SDRAM Controller Compiler 的用户向导-DDR and DDR2 SDRAM Controller Compiler User Guide
Platform: | Size: 1005568 | Author: xl | Hits:

[Windows DevelopDDDRR_SDRAM_cD

Description: DDR SRAM控制器的verilog完整设设计文档(包含有完整的verilog源代码), -DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
Platform: | Size: 476160 | Author: 压榨 | Hits:

[Othermem_interface_top_ddr_controller_0

Description: 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller
Platform: | Size: 8192 | Author: 李成欢 | Hits:

[OtherIXP2400_HardwareRefManual

Description: intel ixp2400 硬件手册,主要包含处理器的相关硬件单元,如ddr 控制器,sram控制器,pci单元等-intel ixp2400 hardware manuals related hardware unit mainly includes a processor, such as ddr controller, sram controller, pci unit, etc.
Platform: | Size: 2732032 | Author: liufeng | Hits:

[VHDL-FPGA-VerilogDDR-SDRAM-Controller

Description: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
Platform: | Size: 262144 | Author: 马龙 | Hits:

[VHDL-FPGA-Verilogddr

Description: ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
Platform: | Size: 4943872 | Author: 松鼠 | Hits:

[hardware designddr_controller

Description: 完整的DDR控制器设计,包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
Platform: | Size: 337920 | Author: zhangbin | Hits:

[Embeded-SCM DevelopDDR_MO

Description: 使用verilog语言实现简单的DDR SDRAM控制器(Using Verilog language to achieve a simple DDR SDRAM controller)
Platform: | Size: 1101824 | Author: 搬砖123 | Hits:
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